Investigating the impact of image content on the energy efficiency of hardware-accelerated digital spatial filters

Battery-operated low-power portable computing devices are becoming an inseparable part of human daily life. One of the major goals is to achieve the longest battery life in such a device. Additionally, the need for performance in processing multimedia content is ever increasing. Processing image and video content consume more power than other applications. A widely used approach to improving energy efficiency is to implement the computationally intensive functions as digital hardware accelerators. Spatial filtering is one of the most commonly used methods of digital image processing. As per the Fourier theory, an image can be considered as a two-dimensional signal that is composed of spatially extended two-dimensional sinusoidal patterns called gratings. Spatial frequency theory states that sinusoidal gratings can be characterised by its spatial frequency, phase, amplitude, and orientation. This article presents results from our investigation into assessing the impact of these characteristics of a digital image on the energy efficiency of hardware-accelerated spatial filters employed to process the same image. Two greyscale images each of size 128 × 128 pixels comprising two-dimensional sinusoidal gratings at maximum spatial frequency of 64 cycles per image orientated at 0° and 90°, respectively, were processed in a hardware implemented Gaussian smoothing filter. The energy efficiency of the filter was compared with the baseline energy efficiency of processing a featureless plain black image. The results show that energy efficiency of the filter drops to 12.5% when the gratings are orientated at 0° whilst rises to 72.38% at 90°

CORBYS cognitive control architecture for robotic follower

In this paper the novel generic cognitive robot control architecture CORBYS is presented. The objective of the CORBYS architecture is the integration of high-level cognitive modules to support robot functioning in dynamic environments including interacting with humans. This paper presents the preliminary integration of the CORBYS architecture to support a robotic follower. Experimental results on high-level empowerment-based trajectory planning have demonstrated the effectiveness of ROS-based communication between distributed modules developed in a multi-site research environment as typical for distributed collaborative projects such as CORBYS

The impact of surgical delay on resectability of colorectal cancer: An international prospective cohort study

AIM: The SARS-CoV-2 pandemic has provided a unique opportunity to explore the impact of surgical delays on cancer resectability. This study aimed to compare resectability for colorectal cancer patients undergoing delayed versus non-delayed surgery. METHODS: This was an international prospective cohort study of consecutive colorectal cancer patients with a decision for curative surgery (January-April 2020). Surgical delay was defined as an operation taking place more than 4 weeks after treatment decision, in a patient who did not receive neoadjuvant therapy. A subgroup analysis explored the effects of delay in elective patients only. The impact of longer delays was explored in a sensitivity analysis. The primary outcome was complete resection, defined as curative resection with an R0 margin. RESULTS: Overall, 5453 patients from 304 hospitals in 47 countries were included, of whom 6.6% (358/5453) did not receive their planned operation. Of the 4304 operated patients without neoadjuvant therapy, 40.5% (1744/4304) were delayed beyond 4 weeks. Delayed patients were more likely to be older, men, more comorbid, have higher body mass index and have rectal cancer and early stage disease. Delayed patients had higher unadjusted rates of complete resection (93.7% vs. 91.9%, P = 0.032) and lower rates of emergency surgery (4.5% vs. 22.5%, P < 0.001). After adjustment, delay was not associated with a lower rate of complete resection (OR 1.18, 95% CI 0.90-1.55, P = 0.224), which was consistent in elective patients only (OR 0.94, 95% CI 0.69-1.27, P = 0.672). Longer delays were not associated with poorer outcomes. CONCLUSION: One in 15 colorectal cancer patients did not receive their planned operation during the first wave of COVID-19. Surgical delay did not appear to compromise resectability, raising the hypothesis that any reduction in long-term survival attributable to delays is likely to be due to micro-metastatic disease

Content driven energy efficiency analysis of hardware accelerated spatial filters for digital image processing

Portable and mobile computing devices that run on batteries such as mobile phones, low-power and ultra-low-power IoT devices, wearable computing devices, wireless video sensor nodes etc. have become an indispensable part of human daily life. One of the major challenges is to have the longest battery life in such devices. Battery life time of the device depends on its energy efficiency which depends on the power consumption of the device. Power consumption of a device can be derived from the rate at which the device consumes energy. Many of these modern devices have touch screens where the content of the applications running in the devices are displayed. Applications running on these devices are dominant in multimedia content including video and images. It has been established that processing image and video content consume more power than any other content. Therefore, these applications involving image and video processing are the major factors in reducing the battery lifetime of such devices. Moreover, the demand on the computing performance of these portable devices is ever increasing. The battery technology and advances in power efficiency of silicon chips used in these devices considerably lag behind the performance enhancements deployed in these portable devices. Energy efficiency optimisation has become an essential objective in the design of modern embedded systems. It is important to mention the three key prevailing technological bottlenecks for high performance computational efficiency gains. These are the memory bottleneck, the Instructional Level Parallelism (ILP) bottleneck and the power bottleneck. The main motivation of this thesis is to address the third bottleneck, the power bottleneck. At the same time, most of the modern portable computing devices contain one or more of System-On-Chip (SoC) type integrated circuits within which there are more than one hardware accelerators implemented to perform dedicated computing functions. The fundamental blocks within the logic circuit are logic gates which are realised from transistors. Dynamic power consumption of a digital logic circuit is directly proportional to the switching of the transistors in the circuit. There are two main factors that affect the switching: the clock frequency and the variation in the input stimulus at the inputs of the circuit. In order to understand the decomposition of the contribution to the power consumption of such a device from the image and video content perspective, it is important to quantify what constitutes the content of a digital image or video. The next step is to find out how these constituent elements impact the power consumption of the device. Digital images are comprised of pixels and these pixels are samples of intensity values represented in binary numbers i.e. 1s and 0s. The variation in the content is represented by the variation in the values of these pixels and vice versa. Image processing mainly involves performing operations on images i.e. in two dimensions. At the sub-symbolic level, the mathematical operations (i.e. convolution operations consisting of Multiplication and Addition, MAC) need to be repeated on the image data numerous times. Accordingly, it remains difficult to achieve real-time performance in software-based implementations of image processing. Therefore, in the modern devices, these operations are accelerated in the bespoke digital circuits in the form of hardware accelerators within the SoCs. In this thesis, the impact of image content on the power consumption and energy efficiency of the most commonly used hardware accelerator architecture for image processing, a spatial filter, is investigated. The first step is to quantify the content of an image into varying frequency sinusoidal gratings of different orientation, phase and contrast. This concept is mainly used in the fields of optometry and biological vision. These areas are combined into this research work by creating a dataset of synthetic images whereby the spatial frequency, phase, contrast and orientation of the sinusoidal grating images are controlled to investigate its impact. A semi-automated experimental framework with a configurable library of hardware accelerated spatial filters is developed in order to explore the impact. Multivariate regression is performed on the selected independent variables for the dependent variable and a statistical model is derived that enables estimation of the energy efficiency of hardware accelerated spatial filters. The model enables algorithm designers to explore and evaluate the energy efficiency of their algorithms without actually implementing them into hardware. The model facilitates the design space exploration of spatial filters with energy efficiency as the objective. The results show that even a featureless plain grey image consumes dynamic power when processed in a digital circuit. This is mainly because of the inherent switching present due to the pixels represented in the binary number format. Moreover, the impact of contrast and phase in an image of sinusoidal grating image is not statistically significant. Maximum amount of energy is consumed when the orientation of the sinusoidal grating in the image is at 0 degrees and the least energy is consumed when the orientation is at 90 degrees. This is due to the row-order scanning of the image and the horizontal symmetry of the hardware blocks to store the image rows. The results show that there is statistically significant impact on the energy efficiency of the spatial filter for varying orientation and spatial frequencies present in the image. The energy efficiency of the template spatial filter drops to 12.5% for the maximum spatial frequency 64 cycles per image and O-degree orientation for a given image of a two-dimensional sinusoidal grating of size 128x 128 pixels whereas, for an orientation of 90 degrees, the energy efficiency is 72.38%. This research provides new insights into the impact of an image content on the power and energy consumption of the hardware accelerated image processing function employed to process the image. The findings presented in this thesis contribute new knowledge regarding the impact of image granularities on processing energy consumption and as such these findings will help inform strategies for energy efficiency gains in image processing

Low-Power TinyOS Tuned Processor Platform for Wireless Sensor Network Motes

In this article we describe a low power processor platform for use in Wireless Sensor Network (WSN) nodes (motes). WSN motes are small, battery-powered devices comprised of a processor, sensors, and a Radio Frequency transceiver. It is expected that WSNs consisting of large numbers of motes will offer long-term, distributed monitoring, and control of real-world equipment and phenomena. A key requirement for these applications is long battery life. We investigate a processor platform architecture based on an application-specific programmable processor core, System-On-Chip bus, and a hardware accelerator. The architecture improves on the energy consumption of a conventional microprocessor design by tuning the architecture for a suite of TinyOS based WSN applications. The tuning method used minimizes changes to the Instruction Set Architecture facilitating rapid software migration to the new platform. The processor platform was implemented and validated in an FPGA-based WSN mote. The benefits of the approach in terms of energy consumption are estimated to be a reduction of 48% for ASIC implementation relative to a conventional programmable processor for a typical TinyOS application suite without use of voltage scaling.Enterprise IrelandScience Foundation Irelan

GALS SoC Interconnect Bus for Wireless Sensor Network Processor Platforms

Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stressa-Lago Maggiore, Italy, 11 - 13 March, 2007The purpose of this paper is to present a new System-on-Chip bus designed for the application specific requirements of Wireless Sensor Network (WSN) platforms. The bus is designed to support Globally Asynchronous Locally Synchronous (GALS) systems. The bus is multi-rate with delay tolerance to support Dynamic Voltage and Frequency Scaled (DVFS) sub-systems. Unlike traditional buses, the sub-systems operate as peers, rather than as master-slaves. Lowpower features include clock gating when inactive and burst transfers. The bus supports up to 255 interconnected resources.Enterprise Irelan

Accelerated encryption algorithms for secure storage and processing in the cloud

The objective of this paper is to outline the design specification, implementation and evaluation of a proposed accelerated encryption framework which deploys both homomorphic and symmetric-key encryptions to serve the privacy preserving processing; in particular, as a sub-system within the Privacy Preserving Speech Processing framework architecture as part of the PPSP-in-Cloud Platform. Following a preliminary study of GPU efficiency gains optimisations benchmarked for AES implementation we have addressed and resolved the Big Integer processing challenges in parallel implementation of bilinear pairing thus enabling the creation of partially homomorphic encryption schemes which facilitates applications such as speech processing in the encrypted domain on the cloud. This novel implementation has been validated in laboratory tests using a standard speech corpus and can be used for other application domains to support secure computation and privacy preserving big data storage/processing in the cloud

Situation assessment through multi-modal sensing of dynamic environments to support cognitive robot control

Awareness of emerging situations in a dynamic operational environment of a robotic assistive device is an essential capability of such a cognitive system, based on its effective and efficient assessment of the prevailing situation. This allows the system to interact with the environment in a sensible (semi)autonomous / pro-active manner without the need for frequent interventions from a supervisor. In this paper, we report a novel generic Situation Assessment Architecture for robotic systems directly assisting humans as developed in the CORBYS project. This paper presents the overall architecture for situation assessment and its application in proof-of-concept Demonstrators as developed and validated within the CORBYS project. These include a robotic human follower and a mobile gait rehabilitation robotic system. We present an overview of the structure and functionality of the Situation Assessment Architecture for robotic systems with results and observations as collected from initial validation on the two CORBYS Demonstrators